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code-of-OV7670PFIFOP3.0TFT
- OV7670+FIFO+3.0TFT的源码和详细描述-code and annotation of OV7670+FIFO+3.0TFT
fifo
- VHDL code for DATA PATH for performing A=A+3 and A=B+C TO DESIGN AND SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
fifo
- Generic c code for Fifo (first in first out), meant for embedded development. It can point to generic structures.-Generic c code for Fifo (first in first out), meant for embedded development. It can point to generic structures.
SLAVE-FIFO-16BITS
- EZUSB FX2 的 SLAVE FIFO例程，包含8051的Firmware以及FPGA的FIFO控制代码-EZUSB FX2 the SLAVE FIFO example, including 8051 MCU Firmware and FPGA FIFO control code
gpif_to_extfifo-fifo-rw
- USB GPIF 接口编程源码，经过验证-The source code for USB GPIF. It was verifed.
code
- 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
FIFO-verilog-CODE
- FIFO存储器的Verilog设计与实现-FIFO verilog CODE
fifo
- FIFO源码以及测试文件基于ISE14，Verilog语言编写，全部工程。-FIFO based on source code and test files ISE14, Verilog language, the whole works.
FIFO
- FIFO test code:FIFO read and write app. read FIFO and save in file, write file to FIFO.-FIFO test code:FIFO read and write app. read FIFO and save in file, write file to FIFO.
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
FIFO
- vhdl code for FIFO implementation
CYUSB3014 Example Code
- Slave fifo 4 flags example
fifo
- 关于FIFO的verilog源代码,可以很快的对FIFO做简单的了解-Verilog on the FIFO source code, you can quickly do a simple understanding of FIFO
FIFO
- first input and first output vhdl code
uart
- 此代码运行MPLab中，pic芯片，串口收发代码，带中断机制-PIC uart leve4 FIFO code
cn554683
- microchip MCU can fifo code-microchip MCU can fifo code
RC_A7125_x3-Reference-code
- 笙科2.4G芯片A7125通信驱动代码，采用直接访问FIFO的方式完成。-Ammiccom 2.4G chip A7125 communication driver code, the use of direct access to the FIFO to complete.
FIFO_ASY
- 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
CCD_Array
- Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
带FIFO的ov7670 FPGA应用程序，经测试可用
- 这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)